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document no. doc-13241-3 www.psemi.com page 1 of 14 ?2012-2013 peregrine semiconductor corp. all rights reserved. rf1 rf2 rfc cmos control driver esd esd esd ctrl ctrl or v dd the PE42359 ultracmos ? rf switch is designed to cover a broad range of applications from 10 mhz through 3 ghz. this reflective switch integrates on-board cmos control logic with a low voltage cmos-compatible control interface, and can be controlled using either single-pin or complementary control inputs. using a nominal +3-volt power supply voltage, a typical input 1 db compression point of +33.5 dbm can be achieved. PE42359 also meets the quality and performance standards for automotive applications and has received aec-q100 grade 2 certification. the PE42359 is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on- insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. product specification spdt ultracmos ? rf switch 10 mhz ? 3 ghz product description figure 1. functional diagram PE42359 features ?? aec-q100 grade 2 certified ?? supports operating temperature up to +105c ?? single-pin or complementary cmos logic control inputs ?? low insertion loss ?? 0.35 db @ 1000 mhz ?? 0.50 db @ 2000 mhz ?? isolation of 30 db @ 1000 mhz ?? high esd tolerance of 2kv hbm ?? typical input 1 db compression point of +33.5 dbm ?? 1.8v minimum power supply voltage ?? small sc-70 package figure 2. package type ? ? 6 \ lead ? sc \ 70 ? doc-02109
product specification PE42359 page 2 of 14 ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-13241-3 ultracmos ? rfic solutions notes: 1. device linearity will begin to degrade below 10 mhz 2. high frequency performance can be improved by external matching (see figure 20 through figure 25 and figure 28) 3. the dc transient at the output of any po rt of the switch when the control voltage is switched from low to high or high to l ow in a 50 ? test set-up, measured with 1ns risetime pulses and 500 mhz bandwidth table 1. electrical specifications @ +25c, v dd = 3.0v (z s = z l = 50 ? ) parameter conditions minimum typical maximum units operation frequency 1 10 3000 mhz insertion loss 2 10-1000 mhz 1000-2000 mhz 2000-3000 mhz 2 0.35 0.50 1.1 0.45 0.60 1.3 db db db isolation - rfx to rfx 10-1000 mhz 1000-2000 mhz 2000-3000 mhz 32 20 13 35 21 14 db db db isolation - rfc to rfx 10-1000 mhz 1000-2000 mhz 2000-3000 mhz 28 19 12 29 20 13 db db db return loss - rfx to rfc 2 10-1000 mhz 1000-2000 mhz 2000-3000 mhz 2 21 15 9 25 18 11 db db db switching time 50% ctrl to 90% or 10% rf 2 us video feedthrough 3 15 mv pp input 1 db compression 1000 mhz @ 2.3 - 3.3v 1000 mhz @ 1.8 - 2.3v 2500 mhz @ 2.3 - 3.3v 2500 mhz @ 1.8 - 2.3v 31.5 29.5 28.5 28 33.5 30.5 30.5 29 dbm input ip3 2500 mhz, 20 dbm input power 55 dbm table 1a. electrical specifications @ -40c to +105c, v dd = 3.0v (z s = z l = 50 ? ) parameter conditions minimum typical maximum units operation frequency 10 3000 mhz insertion loss 10-1000 mhz 1000-2000 mhz 2000-3000 mhz 0.35 0.5 1.1 0.6 0.75 1.4 db db db isolation - rfx to rfx 10-1000 mhz 1000-2000 mhz 2000-3000 mhz 31 19 12 35 21 14 db db db isolation - rfc to rfx 10-1000 mhz 1000-2000 mhz 2000-3000 mhz 27 18 11 29 20 13 db db db return loss - rfx to rfc 10-1000 mhz 1000-2000 mhz 2000-3000 mhz 20 14 9 25 18 11 db db db switching time 50% ctrl to 90% or 10% rf 3.6 us video feedthrough 15 mv pp input 1 db compression 1000 mhz @ 2.3 - 3.3v 1000 mhz @ 1.8 - 2.3v 2500 mhz @ 2.3 - 3.3v 2500 mhz @ 1.8 - 2.3v 30.5 28.5 27.5 27 33.5 30.5 30.5 29 dbm input ip3 2500 mhz, 20 dbm input power 54 dbm
product specification PE42359 page 3 of 14 document no. doc-13241-3 www.psemi.com ?2012-2013 peregrine semiconductor corp. all rights reserved. 0 5 10 15 20 25 30 35 40 0 500 1000 1500 2000 2500 3000 input ? power ? [dbm] frequency ? [mhz] (vdd ? = ? +3.3v) t= ? +25c t= ? +105c table 2. pin descriptions electrostatic discharge (esd) precautions when handling this ultracmos ? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. figure 3. pin configuration (top view) pin no. pin name description 1 rf1 1 rf port1 2 gnd ground connection. traces should be physically short and connected to ground plane for best performance. 3 rf2 1 rf port2 4 ctrl switch control input, cmos logic level. 5 rfc 1 rf common 6 ctrl or v dd this pin supports tw o interface options: single-pin control mode . a nominal 3-volt supply connection is required. complementary-pin control mode . a com- plementary cmos control signal to ctrl is supplied to this pin. bypassing on this pin is not required in this mode. table 4. absolute maximum ratings symbol parameter/conditions min max units v dd power supply voltage -0.3 4.0 v v i voltage on any dc input -0.3 v dd + 0.3 v t st storage temperature range -65 150 c t op operating temperature range -40 105 c p in 1 input power (50 ? ) see fig. 4 v esd,hbm esd voltage hbm 2 , all pins 2000 v v esd,cdm esd voltage cdm 3 , all pins 1000 v table 3. operating ranges parameter min typ max units v dd power supply voltage 1.8 3.0 3.3 v i dd power supply current (v dd = 2.3 to 5.5v [+25c only]) 9 20 a control voltage high 0.7x v dd v control voltage low 0.3x v dd v figure 4. maximum power handling exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. moisture sensitivity level the moisture sensitivity level rating for the PE42359 in the sc70 package is msl1. note 1: all rf pins must be dc blocked with an external series capacitor or held at o vdc notes: 1. to maintain optimum device performance, do not exceed max p in at desired operating frequency (see figure 4 ) 2. human body model (mil_std 883 method 3015) 3. charged device model (jedec jesd22-c101)
product specification PE42359 page 4 of 14 ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-13241-3 ultracmos ? rfic solutions control voltages signal path pin 6 (v dd ) = v dd pin 4 (ctrl) = high rfc to rf1 pin 6 (v dd ) = v dd pin 4 (ctrl) = low rfc to rf2 table 5. single-pin control logic truth table table 6. complementary-pin control logic truth table control voltages signal path pin 6 ( ctrl or v dd ) = low rfc to rf1 pin 6 ( ctrl or v dd ) = high pin 4 (ctrl) = low rfc to rf2 control logic input the PE42359 is a versatile rf cmos switch that supports two operating control modes; single-pin control mode and complementary-pin control mode. single-pin control mode enables the switch to operate with a single control pin (pin 4) supporting a +3-volt cmos logic input, and requires a dedicated +3-volt power supply connection on pin 6 (v dd ). this mode of operation reduces the number of control lines required and simplifies the switch control interface typically derived from a cmos ? processor i/o port . complementary-pin control mode allows the switch to operate using complementary control pins ctrl and ctrl (pins 4 and 6), that can be directly driven by +3-volt cmos logic or a suitable ? processor i/o port. this enables the PE42359 to be used as a potential alternate source for spdt rf switch products used in positive control voltage mode and operating within the PE42359 operating limits. latch-up avoidance unlike conventional cmos devices, ultracmos ? devices are immune to latch-up. switching frequency the PE42359 has a maximum 25 khz switching rate.
product specification PE42359 page 5 of 14 document no. doc-13241-3 www.psemi.com ?2012-2013 peregrine semiconductor corp. all rights reserved. figure 5. insertion loss (rfx nominal condition) 1 figure 6. insertion loss vs temp (rf1-rfc) 1 figure 7. insertion loss vs vdd (rf1-rfc) 1 typical performance data @ +25c, v dd = 3.0v unless otherwise specified note 1: high frequency performance can be improved by external matching (see figure 20 through figure 25 and figure 28)
product specification PE42359 page 6 of 14 ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-13241-3 ultracmos ? rfic solutions figure 8. rfc-rfx isolation vs temp figure 9. rfc-rfx isolation vs vdd figure 10. rfx-rfx isolation vs temp figure 11. rfx-rfx isolation vs vdd typical performance data @ +25c, v dd = 3.0v unless otherwise specified
product specification PE42359 page 7 of 14 document no. doc-13241-3 www.psemi.com ?2012-2013 peregrine semiconductor corp. all rights reserved. figure 12. rfc port return loss vs temp (rf1 active) 1 figure 13. rfc port return loss vs vdd (rf1 active) 1 figure 14. rfc port return loss vs temp (rf2 active) 1 figure 15. rfc port return loss vs vdd (rf2 active) 1 typical performance data @ +25c, v dd = 3.0v unless otherwise specified note 1: high frequency performance can be improved by external matching (see figure 20 through figure 25 and figure 28)
product specification PE42359 page 8 of 14 ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-13241-3 ultracmos ? rfic solutions figure 16. active port return loss vs temp (rf1 active) 1 figure 17. active port return loss vs vdd (rf1 active) 1 figure 18. active port return loss vs temp (rf2 active) 1 figure 19. active port return loss vs vdd (rf2 active) 1 typical performance data @ +25c, v dd = 3.0v unless otherwise specified note 1: high frequency performance can be improved by external matching (see figure 20 through figure 25 and figure 28)
product specification PE42359 page 9 of 14 document no. doc-13241-3 www.psemi.com ?2012-2013 peregrine semiconductor corp. all rights reserved. performance comparison @ 25c and v dd = 3.0v with or without matching figure 20. insertion loss rf1 1 figure 22. active port return loss (rf1 active) 1 figure 24. rfc port return loss (rf1 active) 1 \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 insertion ? loss ? ( \ db) frequency ? (hz) x10 9 no ? external ? matching with ? capacitor ? on ? rfc ? line \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 insertion ? loss ? ( \ db) frequency ? (hz) x10 9 no ? external ? matching with ? capacitor ? on ? rfc ? line \ 4.5 \ 4 \ 3.5 \ 3 \ 2.5 \ 2 \ 1.5 \ 1 \ 0.5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 insertion ? loss ? ( \ db) frequency ? (hz) x10 9 no ? external ? matching with ? capacitor ? on ? rfc ? line figure 23. active port return loss (rf2 active) 1 figure 21. insertion loss rf2 1 figure 25. rfc port return loss (rf2 active) 1 \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 return ? loss ? ( \ db) frequency ? (hz) x10 9 no ? external ? matching with ? capacitor ? on ? rfc ? line note 1: high frequency performance can be improved by external matching (see figure 20 through figure 25 and figure 28) \ 4.5 \ 4 \ 3.5 \ 3 \ 2.5 \ 2 \ 1.5 \ 1 \ 0.5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 insertion ? loss ? ( \ db) frequency ? (hz) x10 9 no ? external ? matching with ? capacitor ? on ? rfc ? line \ 40 \ 35 \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 return ? loss ? ( \ db) frequency ? (hz) x10 9 no ? external ? matching with ? capacitor ? on ? rfc ? line
product specification PE42359 page 10 of 14 ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-13241-3 ultracmos ? rfic solutions evaluation kit the spdt switch ek board was designed to ease customer evaluation of peregrine?s PE42359. the rf common port is connected through a 50 ? transmission line via the top sma connector, j1. rf1 and rf2 are connected through 50 ? transmission lines via sma connectors j2 and j3, respectively. a through 50 ? transmission is available via sma connectors j4 and j5. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the board is constructed of a two metal layer fr4 material with a total thickness of 0.031?. the bottom layer provides ground for the rf transmission lines. the transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 0.0476?, trace gaps of 0.030?, dielectric thickness of 0.028?, metal thickness of 0.0021? and r of 4.4. j6 and j7 provide a means for controlling dc and digital inputs to the device. j6-1 is connected to the device v dd or ctrl input. j7-1 is connected to the device ctrl input. figure 26. evaluation board layouts doc-02396
product specification PE42359 page 11 of 14 document no. doc-13241-3 www.psemi.com ?2012-2013 peregrine semiconductor corp. all rights reserved. figure 27. evaluation board schematic t-line description -- mode l = cpwg h=28mils t=2.1mils w=47mils g=30mils er = 4.4 general comments -- transmission lines connected to j1, j2, and j3 should have exactly the same electrical length. the path from j2 to j3 including the distance through the part should have the same length as j4 and j5 and be in parallel to j4 to j5. 1 2 j7 cntl 1 j3 rf2 r1 1kohm r2 1kohm 1 j5 n/ a 1 j4 n/a 1 j2 rf1 1 2 j6 cntlx/vdd 2 gnd 1 rf_1 3 rf_2 4 ctrl 5 rfc 6 vdd u1 PE42359/sc70-6 1 j1 rfc 102-0889
product specification PE42359 page 12 of 14 ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-13241-3 ultracmos ? rfic solutions figure 28. evaluation board schematic with matching t-line description -- mode l = cpwg h=28mils t=2.1mils w=47mils g=30 mils er = 4.4 general comments -- transmission lines connected to j1, j2, and j3 should have exactly the same electrical length. the path from j2 to j3 including the distance through the part shouldhave thesamelengthasj4andj5andbeinparallel to j4 to j5. w=10mil, l=80mil 50 ohm 50 ohm 50 ohm 50 ohm c1 close to right end of tline 1 2 j7 cntl 1 j3 rf2 r1 1kohm r2 1kohm 1 j5 n/ a 1 j4 n/a 1 j2 rf1 1 2 j6 cntlx/vdd 2 gnd 1 rf_1 3 rf_2 4 ctrl 5 rfc 6 vdd u1 PE42359/sc70-6 1 j1 rfc 1 2 c1 0.5pf 102-0925
product specification PE42359 page 13 of 14 document no. doc-13241-3 www.psemi.com ?2012-2013 peregrine semiconductor corp. all rights reserved. 2.100.05 1.250.10 1.30 0.65 0.2250.075 2.100.10 0.900.10 0.050.05 top view side view end view a 0.10 c (2x) c 0.10 c 0.05 c seating plane b 0.10 c (2x) pin #1 corner recommended land pattern 1.90 0.65 0.50 min 1.30 0.40 min 13 6 4 0.360.10 0.1650.085 0.10 a b all features figure 29. package drawing ? ? 6 \ lead ? sc \ 70 ? figure 30. top marking specification ? ppp yww = pin 1 indicator ppp = part number yww = date code doc-01629 doc-01923
product specification PE42359 page 14 of 14 ?2012-2013 peregrine semiconductor corp. all rights reserved. document no. doc-13241-3 ultracmos ? rfic solutions figure 31. tape and reel specifications tape feed direction table 7. ordering information order code description package shipping method PE42359scaa-z PE42359 spdt rf switch 6-lead sc-70 3000 units / t&r ek42359-01 PE42359 evaluation ki t evaluation kit 1 / box advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information for sales and contact information please visit www.psemi.com .

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